1. Field of the Invention
The invention relates to methods for manufacturing semiconductor devices, and more particularly, to methods for manufacturing semiconductor devices that include fin-type channel regions.
2. Description of the Related Art
Field effect transistors have been manufactured with fin channel structures (hereinafter, referred to as fin-FETs) for improving certain device performance parameters in the resulting semiconductor devices. One example of a memory cell utilizing a fin-FET structure is disclosed in U.S. Pat. No. 6,664,582 to David M. Fried et al. (“Fried”) entitled “FIN MEMORY CELL AND METHOD OF FABRICATION,” and another example can be found in U.S. Pat. No. 6,876,042 to Bin Yu et al. (“Yu”) entitled “ADDITIONAL GATE CONTROL FOR A DOUBLE-GATE MOSFET” which discloses a fin-FET including fins formed on an insulation layer.
Because the top surfaces and side surfaces of the fins in a fin-FET can be used as channel regions, fin-FETs can have wider channel regions than planar transistors formed in the same surface area. Accordingly, fin-FETs can provide increased operation current, thereby providing improved performance relative to corresponding planar transistors.
The fin-FETs disclosed in both Fried and Yu, however, are fabricated using silicon-on-insulator (SOI) substrates in which the fins are insulated from the bulk substrate bodies. Accordingly, the threshold voltage of the fin-FET transistors cannot be effectively controlled using body-bias, thereby complicating efforts to control the threshold voltage of the resulting CMOS transistors. However, if a conventional bulk substrate is used to allow for more effective body-bias control, the resulting increase in the extent of the drain depletion region tends to increase a junction leakage current, off current, and junction capacitance, thereby degrading the performance of the semiconductor devices. In addition, in highly integrated devices, there tend to be additional deceases in threshold voltage and corresponding increases in off current as a result of short channel effects.
Another problem associated with fin-FETs is high contact resistance. According to Fried, for example, the fin-FET includes bit line contacts formed across and contacting the top surfaces of the fins. However, because the bit lines contact only the narrow top surfaces of the fins, the resistance of these bit line contacts may be very high and will tend to degrade the performance of the resulting devices. The configuration of the fins may be modified, for the example, the fins may be bent, in order to increase the area available for forming the bit line contacts and reduce the contact resistance. Reconfiguring the fin structure, however, tends to increase the complexity of the semiconductor device fabrication, thereby increasing costs and tending to suppress yield.
According to Yu, the sizing of the source and drain regions in contact with fins may be increased to provide greater contact area. However, as the distance between the fins is increased to accommodate the enlarged source and drain regions, the overall degree of integration of the resulting fin-FET device will be reduced.
Another problem associated with fabricating fin-FETs is damage to and/or collapse of the thin fins protruding from a substrate. The likelihood of such damage or collapse increases as the widths of the fins is reduced. For example, as illustrated in Fried, elongated fins project from the substrate and are not initially provided with any supporting or reinforcing structures. Accordingly, forming the fins as suggested by Fried produces fin structures that are susceptible to mechanical damage and which may collapse or suffer damage during subsequent fabricating processes.